Serial data transmission systems often are adopted as high speed data transmission methods to overcome the limits of data transmission rates of conventional parallel data transmission systems. Generally, a serial data transmission system adopts a differential signal structure to increase noise immunity and uses current mode structure in the transmitter to support various voltage swings with common mode voltage level requirements. The voltage swing and common mode voltage level in the current mode differential pair generally depend on the tail current source, and the accurate bias current through using the tail current source in order to meet the specifications of the voltage swing and common mode level. In such a serial data interface, signal integrity often can depend on the matching between the transmitter and receiver's termination impedances. Without accurate impedance matching the signal propagated from the transmitter to the receiver can experience significant undesirable distortion due to reflected waves as the bit error rate of data transmission increases.
Considering PVT (Process, Voltage and Temperature) variations in semiconductor manufacturing of serial data transmission systems, where PVT corners represent the extremes of these parameter variations within which a circuit must function correctly, it will be appreciated that a circuit running on devices fabricated at these process corners may run slower or faster, and at lower or higher temperatures and voltages than specified. Thus, in light of PVT variations it is not practicable to design a system on the assumption that there are no variations in voltage swing, common mode voltage level and impedance. Although the variation of the termination impedance can be reduced through calibration techniques, the variations in voltage swing and common mode voltage can still occur due to the variations from the tail current source of the differential pair.
One conventional solution to prevent current tail variation from voltage swing and common mode voltage variation is to use a cascoded-structured current mirror. The cascoded structure may be constructed from two transistors such as NMOS (n-type metal oxide semiconductor), with one operating as a common emitter or common source and the other as a common base or common gate. Such a conventional cascoded-structure may be duplicated for each leg of current mirrored differential pair. In such a configuration, the tail current has large output impedance by virtue of stacked transistors and the current becomes relatively insensitive to common mode voltage variation. However, such cascoded-structures require greater headroom margin, which effectively limits the achievable maximum voltage swing. In general, the differential voltage swing of high speed serial data transmission is 0.4V˜1.2V and in such a large voltage swing mode, the compensation circuit incorporating the stacked transistors can suffer from a lack of voltage headroom. The lack of headroom can become severe when PVT variations result in an extreme slow process speed with low voltage; thereby, diminishing the usefulness of this solution in serial data transmission systems.
Thus, the need exists for a way to reduce or eliminate the effects of variations from the tail current source in serial data transmission systems for situations involving PVT variations.